1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device having a recess channel structure therein.
2. Description of Related Art
As a dimension of a MOSFET (metal-oxide-semiconductor field effect transistor) device is getting smaller, a channel length of a semiconductor device becomes shorter as well. Such a short channel length may somehow increase the OFF leakage current of the device. An increase dosage of ion implantation can solve the above-mentioned problem, but this will also increase the leakage current in a storage node junction, and thus shorten data retention time.
One of the known methods for increasing the channel length effectively is to apply a recess channel structure to a MOSFET device.
FIGS. 1A to 1E are schematic cross-sectional views illustrating a process flow of fabricating a conventional MOS (metal-oxide-semiconductor) device having a recess channel structure.
Referring to FIG. 1A, the method of fabricating a MOS device having a recess channel structure includes forming shallow trench isolation structures in a substrate 100, and then forming a recess having a recess channel structure by an etching process. A patterned pad oxide layer 102 and a patterned pad silicon nitride layer 104 are initially formed on the substrate 100. An etching process is performed for forming trenches 106 in the substrate 100 by using the patterned pad silicon nitride layer 104 as an etching mask. An insulation material fills the trenches 106 to form shallow trench isolation structures 108. After the shallow trench isolation structures 108 are formed, a patterned hard mask layer 110 and a patterned photoresist layer 112 are formed on the substrate. The patterned hard mask layer 110 and the patterned photoresist layer 112 have an opening 114. The opening 114 exposes a portion of the patterned pad silicon nitride layer 104 and the adjacent insulation layer of the shallow trench isolation structures 108.
Referring to FIG. 1B, a first etching process is performed, using the patterned photoresist layer 112 as an etching mask, to remove the exposed patterned silicon nitride layer 104 and the adjacent insulation layer of the shallow trench isolation structures 108 so as to form a recess 116. The bottom of the recess 116 is supposed to be at a position depicted by the dotted line 118, which is predetermined to be a recess channel. However, after the first etching process, the recess 116 formed can not reach the original position shown by the dotted line 118 (i.e. the predetermined recess channel). Silicon horns 100a remain above the dotted line in the substrate 100.
Referring to FIG. 1C, a CDE (corner device extent) process is performed to remove the silicon horns 100a because the silicon horns 100a tend to lower the breakdown voltage and cause the leakage current problems. A CDF (corner device formation) process is then performed to remove the insulation layer of the shallow trench isolation structures 108 on sidewalls of the recess 116 so as to form a recess 122 with divots 120. Hence, the recess channel region 118 is exposed, as shown in FIG. 1D. The formation of the divots 120 can improve the performance of the device.
Referring to FIG. 1E, the patterned photoresist layer 112 and the patterned hard mask layer 110 are removed. A gate dielectric layer 124 is formed on the recess channel region 118 of the recess 122. A conductive layer fills into the recess 122 and a patterning process is performed thereon so as to form a gate 126. Thereafter, an ion implant process is performed to form source and drain regions. The source and drain regions are not shown in FIG. 1E because they can only be shown in a different direction.
In the above-mentioned method, the recess 116 extends outwardly to become the recess 122 when the CDF process is performed to form the divots 120. If the recess 122 is excessively extended, the gate 126 may connect with the adjacent contact plugs, such as the contact plugs of the word lines. Ultimately, a short current problem occurred.
To avoid the problem of excessively extending outwardly caused by the lateral over-etching during the CDF process, the insulation layer is usually formed as a sandwich structure including a liner when a conventional shallow trench isolation structure is fabricated. Referring to FIG. 1A, a first silicon oxide layer 108a is formed in the trenches 106. Thereafter, a silicon nitride liner 108b and then a second oxide layer 108c are formed. In the CDF process, the etching proceeds only through the first silicon oxide layer 108a and stops on the silicon nitride liner 108b. Thus, the lateral over-etching problem can be avoided. However, this method requires a plurality of layers of materials, so the process becomes very complicated. Moreover, the thickness of the first silicon oxide layer 108a is so thin that the first silicon oxide layer 108a has high aspect ratio and the depth of the divots 120 is not deep enough after the CDF process. If a deeper depth of the divots 120 is necessarily required, the recess 122 formed may excessively extend outwardly, as shown in FIG. 1D.
Also, if a misalignment occurs during the patterning process of the photoresist layer 112, the position of the patterned photoresist layer 112 may shift. Hence, the depths and sizes of the divots 120 may be different beside the recess channel region 118, and deviations among devices are resulted.